The present invention generally relates to programmable semiconductor read only memory devices. More particularly, the present invention is directed to a programmable semiconductor read only memory device comprising a memory cell array formed by a plurality of memory cells arranged in a matrix arrangement wherein information is positively written into a selected memory cell and a breakdown of insulator layers of non-selected memory cells is prevented from occurring during a write operation.
In a conventional programmable semiconductor read only memory device, there is a programmable read only memory (hereinafter simply referred to as a PROM) of the type wherein information is written into a selected memory cell by melting a fuse of the selected memory cell. However, a breakdown of an insulator for a conduction type PROM (hereinafter simply referred to as a BIC PROM) comprising memory cells each formed by a metal insulator semiconductor field effect transistor (hereinafter simply referred to as a MIS FET) and a capacitor has been recently proposed. In such a BIC PROM, a word line is coupled to a gate of the MIS FET of the memory cell, and a bit line is grounded via the MIS FET and the capacitor of the memory cell. When writing information into a selected memory cell of the BIC PROM, a high voltage is applied to the capacitor of the selected memory cell so as to break down an insulator layer of the capacitor and make the capacitor conductive. According to the BIC PROM, a write operation can be performed within an extremely short time i.e., on the order of several microseconds, and for this reason, the BIC PROM is suited for use in various devices. On the other hand, during the write operation of the BIC PROM, it is necessary to protect the capacitors of non-selected memory cells so that the breakdown of the insulator layers of these capacitors will not occur.
However, when the memory cell array of the BIC PROM is simply controlled by a combination of high-level and low-level voltages, as in the case of a PROM in which the information is written into the memory cell by melting the fuse of the memory cell, there is a possiblity that the MIS FET and the capacitor of the non-selected memory cell may become damaged during the write operation. In addition, there are problems in that the circuit construction of the BIC PROM becomes complex when additional circuits and power sources are provided to protect the non-selected memory cells, and furthermore, the integration density of the BIC PROM becomes poor and the power consumption of the BIC PROM becomes large.
On the other hand, the voltage applied to the selected memory cell of the BIC PROM for breaking down the insulator layer of the capacitor is applied to the capacitor via the MIS FET. For this reason, it is impossible to apply a large voltage to the bit line, since the MIS FET of the selected memory cell will become damaged if the voltage applied to the selected memory cell is greater than a maximum tolerable voltage of the MIS FET. Hence, there is a problem in that a capacitor which must have a large voltage applied in order to break down the insulator layer thereof cannot be used in the BIC PROM. When considering the wide range of applications of the BIC PROM, it is desirable that the information can be written into the selected memory cell even when the capacitor of the selected memory cell requires a large voltage for breaking down the insulator layer thereof, and that the non-selected memory cells are positively protected.